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cy29972 3.3 v, 125-mhz multi-output zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07290 rev. *d revised june 3, 2011 features output frequency up to 125 mhz 12 clock outputs: frequency configurable 350 ps max. output-to-output skew configurable output disable two reference clock inputs for dynamic toggling oscillator or crystal reference input spread-spectrum-compatible glitch-free output clocks transitioning 3.3 v power supply pin-compatible with mpc972 industrial temperature range: ?40 c to +85 c 52-pin thin quad flat package (tqfp) package note 1. x = the reference input frequency, 200 mhz < f vco < 480 mhz. table 1. frequency table [1] vc0_sel fb_sel2 fb_sel1 fb_sel0 f vc0 00008x 000112x 001016x 001120x 010016x 010124x 011032x 011140x 10004x 10016x 10108x 101110x 11008x 110112x 111016x 111120x block diagram ref_sel 0 1 0 1 phase detector vco lpf sync frz d q qa0 sync frz d q sync frz d q sync frz d q sync frz d q sync frz d q 0 1 /2 power-on reset output disable circuitry data generator /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 sync pulse xin xout tclk0 tclk1 tclk_sel fb_in fb_sel2 mr#/oe sela(0,1) 2 selb(0,1) 2 selc(0,1) 2 fb_sel(0,1) 2 sclk sdata inv_clk qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 fb_out sync 12 vco_sel pll_en [+] feedback
cy29972 document #: 38-07290 rev. *d page 2 of 13 contents pin configuration ..............................................................3 pin description...................................................................3 description ........................................................................5 glitch-free output frequency transitions .....................5 sync output .....................................................................6 power management ..........................................................7 absolute maximum ratings............................................. 7 dc parameters ..................................................................8 ac parameters ..................................................................8 ordering information ........................................................ 9 ordering code definition ...... ....................................... 9 package drawing and dimension ................................. 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ............ ..................................... 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ........... ............ 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy29972 document #: 38-07290 rev. *d page 3 of 13 pin configuration vss mr#/oe sclk sdata fb_sel2 pll_en ref_sel tclk_sel tclk0 tclk1 xin xout vdd fb_sel1 sync vss qc0 vddc qc1 selc0 selc1 qc2 vddc qc3 vss inv_clk selb1 selb0 sela1 sela0 qa3 vddc qa2 vss qa1 vddc qa0 vss vco_sel vss qb0 vddc qb1 vss qb2 vddc qb3 fb_in vss fb_out vddc fb_sel0 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 cy29972 pin description [2] pin name pwr i/o type description 11 x in ?i? oscillator input . connect to a crystal. 12 x out ?o? oscillator output . connect to a crystal. 9t clk0 ?ipu external reference/test clock input . 10 t clk1 ?ipu external reference/test clock input . 44, 46, 48, 50 qa(3:0) v ddc o? clock outputs . see table 2 for frequency selections. 32, 34, 36, 38 qb(3:0) v ddc o? clock outputs . see table 2 on page 5 for frequency selections. 16, 18, 21, 23 qc(3:0) v ddc o? clock outputs . see table 2 on page 5 for frequency selections. 29 fb_out v ddc o? feedback clock output . connect to fb_in for normal operation. the divider ratio for this output is set by fb_sel(0:2). see table 1 on page 1 . a bypass delay capacitor at this output will c ontrol input reference/ output banks phase relationships. 25 sync v ddc o? synchronous pulse output . this output is used for system synchronization. the rising edge of the output pulse is in sync with both the rising edges of qa (0:3) and qc(0:3) output clocks regardless of the divider rati os selected. 42, 43 sela(1,0) ? i pu frequency select inputs . these inputs select the divider ratio at qa(0:3) outputs. see table 2 . 40, 41 selb(1,0) ? i pu frequency select inputs . these inputs select the divider ratio at qb(0:3) outputs. see table 2 . 19, 20 selc(1,0) ? i pu frequency select inputs . these inputs select the divider ratio at qc(0:3) outputs. see table 2 . note 2. a bypass capacitor (0.1 mf) should be placed as close as possible to each positive power (< 0.2?). if these bypass capacitors are not close to the pins, their high-frequency filtering characteristics will be c ancelled by the lead inductance of the traces [+] feedback
cy29972 document #: 38-07290 rev. *d page 4 of 13 5, 26, 27 fb_sel(2:0) ? i pu feedback select inputs . these inputs select the divide ratio at fb_out output. see table 1 on page 1 . 52 vco_sel ? i pu vco divider select input . when set low, the vco output is divided by 2. when set high, the divider is bypassed. see table 1 on page 1 . 31 fb_in ? i pu feedback clock input . connect to fb_out for accessing the pll. 6 pll_en ? i pu pll enable input . when asserted high, pll is enabled; when low, pll is bypassed. 7 ref_sel ? i pu reference select input . when high, the crystal oscillator is selected; when low, tclk (0,1) is the reference clock. 8 tclk_sel ? i pu tclk select input . when low, tclk0 is selected and when high tclk1 is selected. 2 mr#/oe ? i pu master reset/output enable input . when asserted low, resets all of the internal flip-flops and also disables all of the outputs. when pulled high, releases the internal flip-flops from reset and enables all of the outputs. 14 inv_clk ? i pu inverted clock input . when set high, qc(2,3) outputs are inverted. when set low, the inverter is bypassed. 3s clk ?ipu serial clock input . clocks data at sdata into the internal register. 4s data ?ipu serial data input . input data is clocked to the internal register to enable/disable individual outputs. this provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 v ddc ? ? ? 3.3 v power supply for output clock buffers. 13 v dd ? ? ? 3.3 v power supply for pll. 1, 15, 24, 30, 35, 39, 47, 51 v ss ? ? ? common ground. pin description [2] pin name pwr i/o type description [+] feedback
cy29972 document #: 38-07290 rev. *d page 5 of 13 description the cy29972 has an integrated p ll that provides low skew and low jitter clock outputs for high-performance microprocessors. three independent banks of four outputs and an independent pll feedback output (fb_out) pr ovide exceptional flexibility for possible output configurations. the pll is ensured stable operation given that the v co is configured to run between 200 mhz and 480 mhz. this allows a wide range of output frequencies up to125 mhz. the phase detector compares the input reference clock to the external feedback input. for normal operation, the external feedback input (fb_in) is connected to the feedback output (fb_out). the internal v co is running at multiples of the input reference clock set by fb_sel(0:2) and vco_sel select inputs (refer to frequency table). the v co frequency is then divided to provide the required output frequencies. these dividers are set by sela(0,1), selb(0,1), selc(0,1) select inputs (see the following table). for situations were the v co needs to run at relatively low frequencies and hence might not be stable, assert vco_sel low to divide the vco frequency by 2. this maintains the desired output relationship s but provides an enhanced pll lock range. the cy29972 is also capable of pr oviding inverted output clocks. when inv_clk is asserted high, qc2 and qc3 output clocks are inverted. these clocks could be used as feedback outputs to the cy29972 or a second pll device to generate early or late clocks for a specific design. this inversion does not affect the output to output skew. glitch-free output fr equency transitions customarily, when output buffers have their internal counters changed ?on the fly,? their output clock periods will: 1. contain short or ?runt? clo ck periods. these are clock cycles in which the cycle(s) are shorte r in period than either the old or new frequencies to which t he cycles are being transitioned. 2. contain stretched clock periods. these are clock cycles in which the cycle(s) are longer in period than either the old or new frequencies to which the cycles are being transitioned. this device specifically includes logic to guarantee that runt and stretched clock pulses do not occu r if the device logic levels of any or all of the following pins changed ?on the fly? while it is operating: sela, selb , selc, and vco_sel. vco_sel sela1 sela0 qa selb1 selb0 qb selc1 selc0 qc 0 0 0 vco/8 0 0 vco/8 0 0 vco/4 0 0 1 vco/12 0 1 vco/12 0 1 vco/8 0 1 0 vco/16 1 0 vco/16 1 0 vco/12 0 1 1 vco/24 1 1 vco/20 1 1 vco/16 1 0 0 vco/4 0 0 vco/4 0 0 vco/2 1 0 1 vco/6 0 1 vco/6 0 1 vco/4 1 1 0 vco/8 1 0 vco/8 1 0 vco/6 1 1 1 vco/12 1 1 vco/10 1 1 vco/8 [+] feedback
cy29972 document #: 38-07290 rev. *d page 6 of 13 sync output in situations where output freque ncy relationships are not integer multiples of each other, the sync output provides a signal for system synchronization. the cy29972 monitors the relationship between the qa and qc output clocks. it provides a low-going pulse, one period in duration, one period prior to the coincident rising edges of the qa and qc outputs. the duration and placement of the pulse depend on the higher of the qa and qc output frequencies. the following timing diagram illustrates various waveforms for the sync output. note that the sync output is defined for all possible combinations of qa and qc outputs, even though under some relationships the lower frequency clock could be used as a synchronizing signal. sync qc qa sync qc qa sync qa qc sync qc qa sync qa qc sync qc qa sync qc qa vco 1:1 mode 2:1 mode 3:1 mode 3:2 mode 4:1 mode 4:3 mode 6:1 mode figure 1. timing diagram [+] feedback
cy29972 document #: 38-07290 rev. *d page 7 of 13 power management the individual output enable/f reeze control of the cy29972 allows the user to implement unique power management schemes into the design. the outputs are stopped in the logic ?0? state when the freeze control bits are activated. the serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. the qc0 and fb_out outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial data. an output is frozen when a logic ?0? is programmed and enabled when a logic ?1? is written. the enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial ?runt? clocks. the serial input register is programmed through the sdata input by writing a logic ?0? start bit followed by 12 nrz freeze enable bits. the period of each sdata bit equals the period of the free running sclk signal. the sdata is sampled on the rising edge of sclk. absolute maximum ratings [5] maximum input volta ge relative to v ss :.............. v ss ? 0.3 v maximum input volta ge relative to v dd :.............. v dd + 0.3 v storage temperature:.. ............... ............... ?65 c to +150 c operating temperature: .............................. ?40 c to +85 c maximum esd protection............................................... 2 kv maximum power supply:................................................ 5.5 v maximum input current: ............................................. 20 ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). notes 3. for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal m eet or exceed these specifications. 4. larger values may cause this device to exhibit oscillator start-up problems. 5. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0-d3 are the control bits for qa0-qa3, respectively d4-d7 are the control bits for qb0-qb3, respectively d8-d10 are the control bits for qc1-qc3, respectively d11 is the control bit for sync start bit table 2. suggested oscillator crystal parameters parameter characteristic min. typ. max. unit conditions t c frequency tolerance ? ? 100 ppm note 3 t s frequency temperature stability ? ? 100 ppm (t a ?10 to +60 c) [3] t a aging ? ? 5 ppm/yr (first 3 years at 25 c) [3] c l load capacitance ? 20 ? pf the crystal?s rated load. [3] r esr effective series resistance (esr) ? 40 80 ohms note 4 [+] feedback
cy29972 document #: 38-07290 rev. *d page 8 of 13 dc parameters v dd = 2.9 v to 3.6 v, v ddc = 3.3 v 10%, t a = ?40 c to +85 c parameter description test conditions min typ max unit v il input low voltage v ss ?0.8 v v ih input high voltage 2.0 ? v dd v i il input low current [6] ? ? ?120 a i ih input high current ? ? 10 a v ol output low voltage [7] iol = 20 ma ? ? 0.5 v v oh output high voltage [7] ioh = ?20 ma 2.4 ? ? v i ddq quiescent supply current ? 10 15 ma i dda pll supply current v dd only ? 15 20 ma i dd dynamic supply current qa and qb at 60 mhz, qc at 120 mhz, cl = 30 pf ? 225 ? ma qa and qb at 25 mhz, qc at 50 mhz, cl = 30 pf ? 125 ? c in input pin capacitance ? 4 ? pf ac parameters v dd = 2.9 v to 3.6 v, v ddc = 3.3 v 10%, t a = ?40 c to +85 c [8] parameter description conditions min typ max unit tr / tf tclk input rise/fall ? ? 3.0 ns fref reference input frequency note 9 ? note 9 mhz fxtal crystal oscillator frequency see table 2 10?25mhz frefdc reference input duty cycle 25 ? 75 % fvco pll vco lock range 200 ? 480 mhz tlock maximum pll lock time ? ? 10 ms tr / tf output clocks rise / fall time [10] 0.8 v to 2.0 v 0.15 ? 1.2 ns fout maximum output frequency q (32) ? ? 125 mhz q (34) ? ? 120 q (36) ? ? 80 q (38) ? ? 60 foutdc output duty cycle [10] tcycle/2 ? 750 ? tcycle/2 + 750 ps tpzl, tpzh output enable time [10] (all outputs) 2 ? 10 ns tplz, tphz output disable time [10] (all outputs) 2 ? 8 ns tccj cycle to cycle jitter [10] (peak to peak) ? 100 ? ps tskew any output to any output skew [10,11] ? 250 350 ps tpd propagation delay [11,12] t clk0 qfb = (38) ?270 130 530 ps t clk1 ?330 70 470 notes 6. inputs have pull-up/pull-down resistors that effect input current. 7. driving series or parallel terminated 50 ? (or 50 ? to v dd/2 ) transmission lines. 8. parameters are guaranteed by design and characterization. not 100% tested in production. 9. maximum and minimum input reference is limited by vc0 lock range. 10. outputs loaded with 30 pf each. 11. 50 ? transmission line terminated into v dd/2 . 12. tpd is specified for a 50-mhz input reference. tpd does not include jitter. [+] feedback
cy29972 document #: 38-07290 rev. *d page 9 of 13 ordering information part number package type production flow cy29972ai 52-pin tqfp indust rial, ?40 c to +85 c CY29972AIT 52-pin tqfp - tape and reel industrial, ?40 c to +85 c pb-free cy29972axi 52-pin tqfp industrial, ?40 c to +85 c cy29972axit 52-pin tqfp - tape and reel industrial, ?40 c to +85 c ordering code definition company id: cy = cypress package type ax = 52-pin tqfp temperature range: x = c or i c = commercial; i = industrial cy base device part number 29972 ax x t t = tape and reel [+] feedback
cy29972 document #: 38-07290 rev. *d page 10 of 13 package drawing and dimension 52-lead thin plastic quad flat pack (10 x 10 x 1.0 mm) a52b 51-85131 *a [+] feedback
cy29972 document #: 38-07290 rev. *d page 11 of 13 acronyms document conventions units of measure acronym description i/o input/output pll phase locked loop tqfp thin quad flat pack symbol units of measure c degree celsius a micro amperes ma milli amperes ms milli seconds mhz mega hertz ns nano seconds pf pico farad ps pico seconds vvolts [+] feedback
cy29972 document #: 38-07290 rev. *d page 12 of 13 document history page document title: cy29972 3.3v, 125-mhz multi-output zero delay buffer document number: 38-07290 rev. ecn no. issue date orig. of change description of change ** 111101 02/07/02 brk new data sheet *a 122882 12/22/02 rbi added power up requirements to maximum ratings *b 387764 see ecn rgl changed the package draw ing and dimension to cypress standard added pb-free devices *c 404340 see ecn rgl minor change: corrected the package diagram *d 3270575 06/03/2011 bash updated as per template updated package diagram 51-85131. added acronyms and units of measure table [+] feedback
document #: 38-07290 rev. *d revised june 3, 2011 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy29972 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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